BogdanVanca

嗨 @vcb1，波纹管是导入档案的指南。1.首先，发射Vitis。2.转到导入 - > Vitis项目导出的ZIP文件 - > Next->导航到项目存档3.进口存档。4.您的工作空间应像图片Bellow 5中的5.转到5EV_BOOT.SPRJ->更改当前项目的目标平台。6。只需单击“确定”。7.点击是。8. Repeat this for all the project and project systems that are existing into the workspace: 5EV_boot: -> 5ev_fsbl.prj, 5ev_pmufw.prj, 5ev_boot.sprj 5ev_hdmi_demo_system: -> 5ev_hdmi_demo.prj, 5ev_hdmi_demo_system.prj.这应该清理.xpfm文件的所有路径。9.验证lscript文件为../src/lscript.ld的路径。该验证应针对5EV_FSBL.PRJ，5EV_PMUFW.PRJ和5EV_HDMI_DEMO.PRJ。10.从每个makefile验证bsplib/lib的路径。 Also verify the XPFM_PATH, if something is wrong go back to step 5. 11. Verify the build configuration. If you are in Debug mode, but you are targeting a release configuration, your paths wont get updated. Go to Manage Configuration-> Verify the active configuration. And I think those are all. Quite a hustle for simply importing a project. I personally recommend the git approach. If you encounter any issues please let me know. Best Regards, Bogdan Vanca

Hi @vcb1, This is the guide for cloning the project and building it from scratch. First you will have to download the git bash for windows from here https://git-scm.com/. After that you go to the fallowing repo: https://github.com/Digilent/Genesys-ZU and copy the repository URL. Chose folder locally on your computer for cloning the repository and launch the fallowing command. Step 1. Clone the project repository and initialize all the submodules. $ git clone git@github.com:Digilent/Genesys-ZU.git Go inside the repository $ cd Genesys-ZU/ Checkout on the 5ev hdmi demo branch. $ git checkout 5ev/demo/hdmi Initialize and update all the submodules branches. $ git submodule init $ git submodule update Change directory to ./sw folder. $ cd sw/ Initialize and update the embeddedsw submodule. $ git submodule init $ git submodule update The detailed procedure is shown bellow. Step 2. Build the project. Launch Vitis with the workspace set to the repository's sw/ws folder. Open XSCT Console through the Xilinx > XSCT Console option in the menu bar at the top of the window. Make sure the current path is correctly set to ../Genesys-ZU/sw/ws Build the project with the fallowing command: source [getws]/../src/checkout.tcl Watch as your workspace gets populated and build. This will take some time.... You can ignore the warnings that are printed on the console. When everything is done you simply have to give a path for the fsbl file, and deploy the project on your board. If you encounter any issues please let me know. When I'm done, I will come back with the second guide for importing the project from the release archive. Best Regards, Bogdan Vanca

Hi @vcb1, Thank you four pointing out this issue. The HDMI demo project reference manual doesn't include our latest workarounds for all the issues created by Vitis when you are trying to import a project. I recommend you to use the guide for the "Hello World Project", //www.knowreader.com/reference/programmable-logic/genesys-zu/demos/hello-world, in which for example I describe in detail how to add relative paths for the linker script. Another issue is indeed related with the path for the *.xpfm file, which needs to be updated immediately after you launch the Vitis app. For that, you simply have to go to each *.sprj and single-click on "Change target platform". Ideally, this will clean up the old project paths. It is quite a struggle to remove all the absolute paths, and Xilinx doesn't really give any help in this direction. A more faster and easier approach would be to simply clone the project repository. You git clone locally, launch Vitis from within the ./ws folder and simply run into the XSCT Console the fallowing command: `source [getws]/../src/checkout.tcl` This will populate your workspace with all the necessary sources and build everything from scratch. More info can be found into the .README file. Right now, I'm trying to replicate all your issues, and I've started an "how-to" guide for building and running the project. I will keep you updated.

Hi @Enthusiastic, Sorry for my late response. I cannot pinpoint anything wrong. Can you also send me a project archive? I will try to verify your setup, together with all your project/source paths. Check bellow: https://docs.xilinx.com/r/en-US/ug1400-vitis-embedded/Export-a-Vitis-Project Make sure that you are including the build files. Thank you. Best Regards, Bogdan Vanca

Hello @Enthusiastic, Can you please clean-up your project, rebuilt-it and after that send me the log file? Best Regards, Bogdan Vanca

Hi @John J, Our latest preset is https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys-zu-3eg/D.0 For now, we don't have any plans to bring in any updates. If you are facing any issues, please let me know. Best Regards, Bogdan Vanca

Hi @John J, Your problem may be caused by not using our custom fsbl file. Our "Hello World" project adds the following https://github.com/Digilent/embeddedsw/tree/6e9e2fa973f2c27d3f979f3c07afdbe616f694a4 repository into the ws. One solution would be to manually clone the embededsw repository, and add it into your Vitis workspace. Xilinx ->Software Repositories-> New-> browse to the repository Note: You need to delete your existing FSBL before you start re-building a new one. Best Regards, Bogdan

Hello @Richm, We found out that there is a "bug" with the "PSU__DDRC__DDR4_ADDR_MAPPING" parameter from the board preset file, that went under our radar. This parameter needs to be disabled in order to return to the static DDR configuration operation in psu_init.c and the FSBL. For that, you need to go to \Xilinx\Vivado\2021.1\data\xhub\boards\XilinxBoardStore\boards\Xilinx\genesys-zu-5ev\C.0 and replace the existent preset file with the one that is attached to this message. After that, open your Vivado project and run in your tcl console the fallowing command: report_property [get_ips design_1_zynq_ultra_ps_e_0_0] -regexp .*PSU__DDRC__DDR4_ADDR_MAPPING.* If the preset was correctly applied, you should see the fallowing message: INFO: [Vivado 12-5777] IP Instance 'design_1_zynq_ultra_ps_e_0_0' cannot be used in a module reference: Property Type Read-only Value CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING string false 0 If not, open your Zynq Ultrascale+ MPSOC IP and go to Presets->Apply Configuration, and browse to the preset that I gave you. Run again the command, and verify if "CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING" is 0. Note: In your project "design_1_zynq_ultra_ps_e_0_0" is the name of the Zynq MPSoc IP. You can find the name of your Zynq MPSOC by running the fallowing command: get_ips and searching for the one that has the "zynq_ultra_ps_e_0_0" extension. If this doesn't solve your issue, please let me know. This change will be available in a future minor revision, but I thought that there is no need to make you wait until we publish it. Best Regards, Bogdan Vanca preset.xml

Hi @Alpha_HW, I will check that out, and I will come back with a response. Best Regards, Bogdan

Hello @Alpha_HW, The OOB demo configures the UART1 interface as EMIO, thus the RX and TX pins are exposed to the PL side. You can connect them to any pins you want. Best Regards, Bogdan Vanca

Hi @QI109, I'm assuming that you are using the 3EG variant. If you want to send data from PL into the DDR4, you simply have to connect your AXI-DMA to one of the HP ports of the ZynqUltrascale+ MPSoC and use an psu_init.tcl file or an fsb.elf file for taking out of reset the A53. For this, you will have to migrate from Vivado to Vitis, where you can use our 3eg_fsbl.elf from our 3EG Hello World Demo, by downloading the corresponding zip file https://github.com/Digilent/Genesys-ZU/releases/tag/3EG%2FHELLO-WORLD%2F2020.1-1. Regarding the High Performance Ports, you can choose between the HP0, HP1, HP2 or HP2 ports as it is shown in the Zynq UltraScale+ Device Technical Reference Manual page 1105 https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf. Thank you, Bogdan Vanca

你好@macellan,那是因为你已经添加ed one. I can see it under the XADC System monitor.

@Fred_HY Here you go. You can find in the attachment a boot bin with the project. You only have to copy the BOOT.bin on an SD card and move the jumper on SD. If it's not working, you have hardware issues. Bellow is a link with the entire project. It has been tested and upgraded to 2019.1. https://www.dropbox.com/s/eyy5lq4tp48usg8/2019_1.rar?dl=0 BOOT.rar

Hello @Fred_HY, No, I didn't forgot. The project is just building.

Hello @Fred_HY, I will send you a boot.bin with the project. Do you have an SD card? If not, I will assist you on programming the flash memory.