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Hello everyone, I am trying to establish a CAN connection between 2 FPGA boards (Zedboard and GenesysZU 3EG) using 2 PMOD CANs. I have used Zynq7 and Zynq Ultrascale+ MPSOC. One of the boards is a transmitter and hence is running the TX.c code from the given examples and the other board is running the RX.c code. When both the codes are run as is, the reception of the message does not occur. And the sending also stops after 1 iteration (perhaps some of the flags are not getting cleared correctly). However, when I change the configuration of the PMOD CAN to CAN_ModeListenOnly from CAN_ModeNormalOpertion in the RX.c code, I am able to receive the sent message, which is getting printed multiple times and the message being received is not the same as the message being sent. All the fields are different including the message ID and dlc. Also, the multiple messages printed are not consistent with each other. Attaching the screenshots of the sending and receiving serial port outputs for your reference. Could this be due to different endianness of the two processors used on the two different boards?

Thank you for the reply. Ya, I think even I will have to do a little digging around apart from the steps mentioned in the guide. Appreciate your inputs.

Hi, Apologies for the late reply. Attaching the log file generated. .log

Hi, Thank you so much for your reply. I have followed exactly the same steps mentioned in the above link. I have performed the last 4 steps to tackle the error message of missing fsbl.elf file that you mentioned in the reply above. The error I am encountering occurs when I build the master_system project (Last step of the "Build a Vitis Application"), even after I am changing the linker path to " ../src/lscript.ld"

Hi everyone, I am working on Digilent Genesys zu-3eg zynq ultrascale+ MPSOC board. I was trying to run the basic hello world program which is provided by Digilent- //www.knowreader.com/reference/programmable-logic/genesys-zu/demos/hello-world?redirect=1 In the final step of "Build a Vitis application" where we are building the master_system project, I am encountering the following error : Could someone please help with the above issue. Thank you

Alright. I will try this approach. Thank you so much!!

Hi everyone, I want to use PMOD CAN with Genesys ZU 3EG Zynq ultracscale+ MPSOC board. I want to know if the data captured by PMOD CAN includes the timestamp with the CAN data frames? Or is there a way to include time stamps with the CAN data frames received. I am using Vivado design suite for designing the system. Thank you

Thank you so much

Hi everyone, I want to use PMOD CAN with Genesys ZU 3EG Zynq ultracscale+ MPSOC board. I want to know if the data captured by PMOD CAN includes the timestamp with the CAN data frames? Or is there a way to include time stamps with the CAN data frames received. I am using Vivado design suite for designing the system. Thankyou

Hi everyone, I am working on Digilent Genesys zu-3eg zynq ultrascale+ MPSOC board. While reading the documentation, I found that the initial Vivado/SDK/Petalinux version supported by Digilent for Genesys ZU-related projects was 2019.1. However, I cannot find any support for vivado 2019.1 version. On the github page, support is available for Vivado 2020.1. Can anyone please let me know where can I find the demo projects with vivado 2019.1 for this board . Thank you