Using Genesys Zu with AXI DMA to send data from PL to DDR4 RAM

[QI109]

The Genesys Zu board comes with DDR4 RAM which I have tried to use integrate with DMA but without any luck. My end goal is to send binary data from the PL fabric into the DDR4 RAM independent of the APU. May someone provide me with a list of things that need to be changed for the AXI DMA IP Core and the Zynq UltraScale+ MPSoC in order to accomplish this?

I especially need instructions on how to configure the SoC for DMA because there is clear documentation on the AXI DMA IP Core but not the SoC for DMA purposes. I have already set up the AXI DMA register space correctly, but I do not know the SoC's AXI ports well. They only show up on Vivado Re-customize IP as highly abstracted out ports. I am guessing the main issue is not having the right high performance AXI interfaces enabled on the SoC.

Edit 1: I came back to clarify that I am running bare metal C programs, if it matters.

EditedAugust 19, 2021by QI109

[JColvin]

Hi@QI109,

I have reached out to another engineer more familiar with the Genesys ZU regarding your question. As a clarification question, are you using the 3EG or the 5EV variant of the Genesys ZU?

Thank you,
JColvin

[BogdanVanca]

Hi@QI109,

I'm assuming that you are using the 3EG variant.

If you want to send data from PL into the DDR4, you simply have to connect your AXI-DMA to one of the HP ports of the ZynqUltrascale+ MPSoC and use an psu_init.tcl file or an fsb.elf file for taking out of reset the A53. For this, you will have to migrate from Vivado to Vitis, where you can use our 3eg_fsbl.elf from our 3EG Hello World Demo, by downloading the corresponding zip filehttps://github.com/Digilent/Genesys-ZU/releases/tag/3EG%2FHELLO-WORLD%2F2020.1-1。对于高性能的港口,你可以choose between the HP0, HP1, HP2 or HP2 ports as it is shown in the Zynq UltraScale+ Device Technical Reference Manual page 1105https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf.

Thank you,

Bogdan Vanca