Vivado和Vitis之间有什么不同？

Xilinx’sVivadoDesign Suite2012年首次亮相是嵌入式开发的集成设计环境。最近，该半导体公司发布了Vitisplatform, which subsequently also includes Vivado, but also enables a broader range of new developers to design hardware. Seeing as how both of these offerings are for embedded development, both are from the same company, and heck, they both start with a “V”, we thought it would be helpful to spend a bit of time differentiating between the two tools.

What Do Vitis and Vivado Both Do?

我们将首先获得大的共同点 - Vitis和Vivado都用于创建在FPGA上运行的设计。

Speak the Right Language

Vivado用于创建在FPGA中运行的硬件设计。这些要么由一组硬件说明语言（HDL，通常是Verilog或VHDL）文件组成，要么由块设计组成，其中可能包括各种预构建的IP块（在其核心抽象中，预先编写的HDL）。如果设计包含处理器，则还需要Vitis编写程序以在处理器上运行，因为Vivado只能处理可编程逻辑。

Vitis is for writing software to run in an FPGA, and is the combination of a couple of different Xilinx tools, including what was Xilinx SDK, Vivado High-Level Synthesis (HLS), and SDSoC. The functionality of each of these is now merged together under Vitis. To break each of these down:

1. Xilinx SDK（Vitis）：写C/C ++以在您在Vivado创建的设计中运行。该代码通常最终至少部分用于配置和控制硬件设计的元素 - 比硬件部分更容易重建，调整和调试。
2. VivadoHLS (Vitis HLS): Write C/C++ to be built into a block which you can include in a Vivado project. This block can often be reused in multiple projects, and even potentially be loaded up in Vivado for manual optimization.
3. SDSoC (Vitis): Write C/C++ to be built into a block which the tool stitches into a previously created Vivado design. You take a platform with some I/O built in, and start accelerating certain data processing functions of your software design by building them into the hardware (while still writing them in software languages).

不同人的不同过程

While the differences in languages are pretty cut and dry, the thought processes present more of a gray area. Both Vivado and Vitis can be used to create the highly-parallel hardware designs that run in FPGA fabric. Vitis also handles the part that runs sequentially in a processor. Parallel and sequential designs each have different snags that you can run into, though. For one, parallel hardware can introduce problems with one particularly slow part of a design effectively slowing down the entire design, even when that specific part is only very rarely used. In software, you would just have rare instances of the process running a bit slower, in hardware, you might have to run your clock slower than you’d like.

Notably, for debugging, when using pure hardware, you aren’t able to just run the design on the device and inspect any part of the design you’d like, as you are often able to with software. Debugging circuits (sometimes internal logic analyzers, sometimes an external logic analyzer) have to be specifically built into the hardware (the latter must be used through an external port), which can potentially slow it down. In addition, you still have to get all of that debug data out of the circuit and back to your PC, though hardware simulation (in Vivado or with other tools) helps with this.

另一方面，只要您构建调试，可以通过软件进行调试。您可以检查存在的任何变量或内存地址，而无需在构建之前定义要查看的内容。Vitis还允许模拟和仿真用软件语言编写的硬件作为附加功能。

The Verdict

Xilinx的两个开发环境都有其用途，尽管如果您同时设计了硬件和软件，则Vitis是一种使用。对于应用程序程序员来说，使用代码配置硬件，而不必潜入VHDL或Verilog的较重语言也更容易接近。您会很高兴知道，Vitis的免费网络下载还包括Vivado作为工具链的一部分，如果您仍然希望以后使用Vivado进行更精细的方法。

Here’s a link using the Genesys ZU with Vitis. Also, note that many of our projects in the参考中心/Wikihave been migrated to Vitis.