~~ TechArticle ~~ ===========添加Zynq Ultrascale处理器到块设计=======================系统，或PS。它必须用于想要连接到处理器的块设计中，并配置PS侧外围设备，时钟和其他设置。//**注意：** //本节仅适用于具有Zynq的板Ultrascale+ Chip.//-----在框图窗格的工具栏中，单击**添加IP ** button（{{：Learn：programable-logic：tutorials：2020.1：add-zynq processor：add-ip.png.png？nolink |}}）。---- <wrap group> <wrap列在弹出窗口中的一半>，搜索并双击** zynq ultrascale+ mpsoc **。</wrap> <wrap列半> {{：学习：可编程逻辑：教程：2020.1：add-ultrascale-zynq-processor：add-zynq-ultra.png？600 |}}}}---- <wrap group> <wrap列半>单击**在设计辅助横幅（绿色条）中运行块自动化**。</wrap> <wrap列半> {{：学习：可编程逻辑：教程：2020.1：add-ultrascale-zynq处理器：run-block-automation-1.png？600 |}}}} </wrap> </wrap> </Wrap> ---- <Wrap group> <包装列在对话框中弹出的一半>确保//应用板预设//已检查。这将将预设配置从板文件应用于IP，从而节省了很多时间，并防止了完全手动进行配置的潜在问题。单击**好的**继续。 </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-ultrascale-zynq-processor:run-block-automation-2.png?600 |}} </WRAP> </WRAP> ---- The needs of your project may require that you change some of the default settings of the PS. To edit its settings, double click on it to open the configuration wizard. Two specific cases are highlighted below: ---- <WRAP group> <WRAP column half> The PS can generate multiple clocks that are then provided to the FPGA fabric. These clocks are referred to as PL clocks, and can be found in the **Clock Configuration** tab of the MPSoC configuration wizard. They are located under the //Low Power Domain Clocks// -> //PL Fabric Clocks// dropdowns. They can be enabled (or disabled) with a checkbox, the hardware source used to drive the clock can be changed, and the frequency can be modified. Board files for Digilent Zynq UltraScale boards enable at least one low power domain PL clock by default, which is intended to be used with peripherals connected to the MPSoC's M_AXI_HPM0_LPD port. Some designs may require additional clocks of specific frequencies be added to your design. In these cases, enable a second clock and specify the needed frequency, as seen in the image to the right. **Note:** //This section can always be returned to later, as the addition of an additional clock can be performed any time before the hardware is built.// </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-ultrascale-zynq-processor:add-additional-clock.png?600 |}} </WRAP> </WRAP> ---- <WRAP group> <WRAP column half> UltraScale devices can also use interrupts generated in FPGA fabric to trigger interrupts within the Processing System. Interrupt-related settings can be changed within the configuration wizard's **PS-PL Configuration** tab. These interrupts can use the IRQ0 port, which can be found under the //General// -> //Interrupts// -> //PL to PS// dropdowns. To enable this port, the IRQ0 dropdown should be set to "1". </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-ultrascale-zynq-processor:add-interrupt.png?600 |}} </WRAP> </WRAP> ---- <WRAP group> <WRAP column half> While interrupts can be directly connected to the pl_ps_irq0 (IRQ0) port by clicking and dragging from one port to another, some designs may require multiple interrupt sources. In these cases, add a **Concat** IP to your block design, and manually connect it to the pl_ps_irq0 port. Additional input ports can be added to a Concat block through its configuration wizard (opened by double clicking on the IP). </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-ultrascale-zynq-processor:add-interrupt-concat.png?600 |}} </WRAP> </WRAP>