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大家好，我是Mahdi，也是这个论坛的新来者。我要订购Genesys 2 Kintex-7 FPGA开发委员会，在此之前，我有几个问题。1）板带有节点锁/浮动许可证或凭证？如果是这样，有多少人和多长时间？2）购买董事会，我可以通过Gensys 2板上的Vivado模拟/合成并实施我的设计吗？如果不是我该怎么办？购买新产品或下载并安装东西会很好吗？3）支持到期时意味着什么？预先感谢您的帮助，

Hey Everyone, I am designing a project in which i used a custom soft core and LMB Bus, LMB Controller followed by Dual port BRAM for Data and instruction read write operations , The custom soft core is WORD ALIGNED. The problem is that during the post implementation functional simulation the 32 bit Word aligned address that i am sending to the bram memory, the unused bits in the address port of BRAM is considered as 'Z' and hence when i dump the code in the FPGA the address is different(for eg. if i give address as 8000, 8004 its considering it as 2000,2001). The address port of FPGA is observed using ILA core. Hence i am not able to read the memory content form correct location. i found a clue to solving this one in LMB controller which is that the LMB controller masks the unused bits to 'Z' in the address for access to LMB. But if i override the masking as manual and setting it to FFFFFFFF int IP customization, the design is still giving 'Z' for the unused address bits. how can i overcome this problem? Below are the screenshots for the reference Thanks

Hi all! I am thinking of purchasing a genesys 2 Board which has a kintex-7 part on it. I have 3 FPGA boards (started with a small lattice board, then a medium altera board, then got a new laptop and a zynq board) and want to move up significantly from the Arty z-7 (which is still a great board) for some of my projects. The problem is, Im wondering if some FPGAs are too much for some computers with not enough resources? specifically Im worried about synthesis and implementation time. If you put the same design on different sized chips, does the larger chip take longer to synthesize in vivado? Obviously larger designs take longer, but I dont want to buy the board if it is going to be to much for my computer. My current system is running vivado/vitis 2020.1 with dual core i5 and 8 gb DDR4 (laptop from 2017). Not the fastest laptop but it works really well even for the arty z-7010 board. I made a design last nigh which used half the BRAM on the chip and about 1/3 of the PL resources (took about 7 min to synth and implement which I dont consider slow at all). would my system be okay with the genesys 2 board? if it takes a long time its okay I can be patient, I just dont want it to time out or take a half hour to synthesize a few LUTs. thanks, -Dom p.s. Im adding this question to the xilinx forums too and will repost the answer here if i get one.

您好，我买了Zybo-Z7-20评估板。我从存储库下载了DMA项目，并且在EDK中运行良好。到目前为止，一切都很好。但是，当我开始重新运行合成时，合成中存在错误，因为无法合成Zynq部分。以下是合成日志中的错误消息。我将感谢任何人注意到这个错误的人，显示了如何超越它。好像我缺少一些设置文件或文件夹，不确定什么.... ==================================错误log：==========================================/Zybo-Z7-20-DMA-2018.2-1/vivado_proj/Zybo-Z7-20-DMA.runs/system_processing_system7_0_0_synth_1/.Xil/Vivado-7036-Rafi-GamePC//incrSyn/system_processing_system7_0_0.genomesNotDumped": no such file or目录合成优化运行时：时间：CPU = 00:00:14; elapsed = 00:00:33 . Memory (MB): peak = 1045.969 ; gain = 379.242 INFO: [Common 17-83] Releasing license: Synthesis 19 Infos, 101 Warnings, 0 Critical Warnings and 1 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Vivado Synthesis failed INFO: [Common 17-206] Exiting Vivado at Mon Apr 13 07:07:59 2020... ============================ Vivado version: 2018.2