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Hey Everyone, I am designing a project in which i used a custom soft core and LMB Bus, LMB Controller followed by Dual port BRAM for Data and instruction read write operations , The custom soft core is WORD ALIGNED. The problem is that during the post implementation functional simulation the 32 bit Word aligned address that i am sending to the bram memory, the unused bits in the address port of BRAM is considered as 'Z' and hence when i dump the code in the FPGA the address is different(for eg. if i give address as 8000, 8004 its considering it as 2000,2001). The address port of FPGA is observed using ILA core. Hence i am not able to read the memory content form correct location. i found a clue to solving this one in LMB controller which is that the LMB controller masks the unused bits to 'Z' in the address for access to LMB. But if i override the masking as manual and setting it to FFFFFFFF int IP customization, the design is still giving 'Z' for the unused address bits. how can i overcome this problem? Below are the screenshots for the reference Thanks

你好。我的系统时钟在我艺术z7-10董事会是125MHz. When I try to simulate this clk in my test bench with a single port RAM, it does not work, and only outputs zeros, however, the simulation does work with a 6.25MHz clock. I looked at the 7 series memory usage guide, and some other xilinx forums, and thye said the BRAM should be able to run at around 200 MHz, so I am not sure why my simulation doesnt. The first picture is the 6.25MHz clock and everything is running fine. The second picture is the 125MHz clock where nothing happens. Testbench is below and source verilog is attatched. Thanks. I also put this on the xilinx forums but accidently posted it in the wrong catagory, so I will put it here too. `timescale 1ns / 1ps module tb; // this testbench from timing diagram memory uage guide. wire [15:0] DO; reg [10:0] ADDR; reg CLK; reg [15:0] DI; reg EN; reg REGCE; reg RST; reg [1:0] WE; always #4 CLK = ~CLK; BRAM_SP_2048x16 uut(DO,ADDR,CLK,DI,EN,REGCE,RST,WE); initial begin CLK = 0; DI = 16'hDDDD; ADDR = 11'h000; EN = 0; REGCE = 0; RST = 0; WE = 2'b00; #1 EN = 1; #8 DI = 16'hCCCC; ADDR = 11'h00F; WE = 2'b11; #8 ADDR = 11'h07E; DI = 16'hBBBB; WE = 2'b11; #8 ADDR = 11'h08F; DI = 16'hAAAA; RST = 1; WE = 2'b00; #8 ADDR = 11'h020; DI = 16'h0000; RST = 0; EN = 0; #4 $finish; end endmodule 7_series_BRAM_SP.v

Hi everyone, I am currently working with a Zybo Z7010 board on Vivado 2018.3 and am trying to implement a memory access in both reading and writing modes. More precisely, I'd like to enable the user to enter a number of coordinates that define a random waveform (sine table...) and to store it somewhere so that the PL can access it in reading mode and display it through a DAC. Please note that it is essential that the reading process is fast for further applications. Now, have been reading many things but I'm a little confused about the "different types of memories that exist". I'm not sure if I should use the BRAM module, the DDR, SRAM... What are the differences of these components and which one would you suggest to use? Finally, would you have a tutorial that goes through the different steps of the implementation? Thanks a lot, NotMyCupOfTea