Takemasa Tamanuki

Zygot-san and JColvin-san, Many thanks for your clear answers and comments about the XC7K325T-license "sharing" matter. I will take your advice and will contact with AMD/Xilinx to get additional information about this matter. Again, thank you for your continued support. Takemasa Tamanuki

> Yes, the board comes with a voucher for obtaining a node-locked license to create a bitstream file for this device. > These licenses are perpetual and are tied to either a HD ID or MAC ID so you can use them on the PC that is tied to your computer for as long as the PC is operable. Is one Kintex-7, XC7K325T (Genesys2) license also applicable for my business-colleague by “add user” on [Product Licensing] as a “full administrate”? I mean, I purchased Genesys2, Digillent (Kintex-7, XC7K325T) on Oct, 2021, and I registered a license with the voucher for a node-locked device license in the box. Recently, I added user for my business-colleague as a “full administrate” by entering his e-mail-address. Then, my business-colleague obtained some node-locked-licenses and loaded them to his Vivado-2020.2. However, his Vivado does not work for “Generate bitstream” with error-message of [Common 17-345: A valid license was not found for feature 'Synthesis' and/or device 'xc7k325t'....]. Actually, “OEM Kintex-7 FPGA XC7K325T Vivado Design Edition Voucher” is listed on the [Manage Licenses] in my [Product Licensing], however that is not listed in the colleague’s [Product Licensing]. Also, License name of “7K325T” is listed on the [License Manager (View License Status)] in my VIVADO, however, that is not listed in the colleague’s VIVADO. Please let me know how to solve this issue (for normal working without any errors of bitstream-generating on the colleague’s VIVADO.). I would appreciate if you could give me your kind advice.

Hi, JColvin-san, Thanks again for your detail comments. > - Is the Genesys 2 powered on with a 12V power supply? Yes. >- Did you install the cable drivers as part of the Vivado download (it was a checkable box); if not you can install them Since I did not install it, I installed it this time. Install-file: “install_digilent.exe” on C:\Xilinx\Vivado\2020.2\data\xicom\cable_drivers\nt64\digilent Install to: C:\Program Files (x86)\Digilent (see attached figs. ) > In the Windows Device manager, when you connect the Genesys 2 to the host computer, does "USB Serial Converter" appear in the with a Bus Reported Device Description of "Digilent USB Device", much like in the screenshot on this post, “Digilent Adept USB Device” (<-- “Not Digilent USB Device”) are shown in the USB Serial Converter A and B, respectively (see attached figs.). However, still same error-message of [Labtools 27-2269] No devices detected on target localhost:………… is shown. I would appreciate your advice to solve it. Thanks. T. Tamanuki

Hi, JColvin-san, Many thanks for your detail comments. Actually, I e-mail received lic-file from Xilinx. (I had not noticed that mail because that was posted in a mail-folder which I don't usually use it.) The lic-file was copied to my Vivado-PC and finally, I success to generate a bitstream-file. However, I can not program the bitstream-file to my Genesys2. I am trying to program by USB (JTAG). My PC is USB-cable connected to the JTAG-port (J17). (as set the JP4=USB, JP5=JTAG). After execute [Open Target], [Auto connect], error is occurred and I can not program it. [Labtools 27-2269] No devices detected on target localhost:………… Also, device is not detected (Number of devices: 0) I would appreciate it if you could give the solutions about this issue. Thanks. T. Tamanuki

嗨,zygot_san,我进入许可。(xxxx-xxxxxx-xxxx-xxxxxxxxx) of Genesys2-voucher into “Have a Voucher to Redeem?”, then push [Redeem Now] on the Product Licensing page, XILINX. However, the synthesis-error of [Common 17-345] is still occurred. Please let me know the solutions about this issue. I did not do the “3. Generate a FLEX license file for your product.” Please let me know this procedure, if my issue is related not to do this procedure. Thanks. T. Tamanuki

Hi, zygot_san, > When you purchased the board you should have received a voucher for a node-locked device license in the box. The license is good for the K325T n other packages as well. Many thanks for your comments. The board will be delivered soon. I will try it.

Genesys2 (xc7k325t) does not work on Vivado 2020.2. I would appreciate it if you could give a comment to solve this issue.

Hello there, Please let me know how do I program Vivado-bitstream-file to QSPI Flash(and SD-memory) on Eclypse-Z7 I made a programing-logic (PL) and generate bitstream-file using Vivado. Then, I make a FSBL-file and create a boot-image file (“BOOT.bin”) using SDK. My program include clocking-wizard IP for 100MHz setting but processing system (PS) is not included. The bitstream works normally on the process of “Program device” of Vivado but does not work thorough the QSPI-flash (or SD-memory). I have tried it using SDK ver. 2016.4 to 2019.1, respectively. “Erase Operation successful.” And “Flash Operation Successful” are shown on the ver.2016.4 to 2017.1 but the program does not work form the QSPI Boot (as well as SD-memory Boot). Also, The “ERROR: Flash Operation Failed” is shown on the ver. 2017.3 to 2019.1. Thanks, T. Tamanuki

Hello again, My problem which I could not implement 100MHz-clock into RTL module is solved. I did newly implement the Clocking-wizard from IP-catalog and add (and revise it as appropriate ) a clocking-wizard-template into V-file as following. ---------------- module Clock_testV1(input sysclk, output pio1, output pio2); reg [0:0] CLK1; wire reset; wire clk_out1; wire locked; always @(posedge clk_out1) begin CLK1 <= CLK1+1'b1; end clk_wiz_0 ( .clk_out1(clk_out1), // output clk_out1 .reset(reset), // input reset .locked(locked), // output locked .clk_in1(sysclk)); // input clk_in1 assign pio1=clk_out1; assign pio2=CLK1; endmodule --------------- 50MHz (and 25MHz) waveform was confirmed by Analog discovery 2 (Oscilloscope displayed waveform is limited by the band-width of AD2 (30MHz).). I would appreciate your comments if my clocking-wizard implement procedure is correct. Fig. 1. Measured waveform (C1(yellow, pio1): 50MHz, C2(blue, pio2): 25MHz).

Hello there, I am trying to introduce 100MHz-clocking into RTL-module instead of the 12MHz-sys-clock. I have made a circuit with connection of [“clk_out1”: Clocking Wizard output] and [pio46: RTL input] (see Fig. 1) and check the pin-out-waveform by the following HDL-statement. (Here, I chose the pio46 as a clock-route since it is clock-dedicated-pin of ”P_MRCC”.) --------------- module Clock_testV1( input pio46, output pio1, output pio2 ); reg [0:0] CLK1; always @(posedge pio46) begin CLK1 <= CLK1+1'b1; end assign pio1=pio46; assign pio2=CLK1; endmodule -------- However, the pio1 (as well as pio2) output did not show pulsed-waveform (but 3.3V continuous DC output, see Fig. 2. C1: yellow, pio1, C2: blue, pio2)). On the other hand, If I replace the “pio46” to “sysclk” in my HDL-statement, it works normally corresponding of 12MHz-clock (see Fig. 3. C1(yellow, pio1): 12MHz, C2(blue, pio2): 6MHz). I would appreciate if you could provide comments to solve (about introduction 100MHz-locking into RTL-module) this issue. PS: I also referred the following sites, but I could not solve my issue. https://forum.digilentinc.com/topic/5325-vivado-clock_dedicated_route/ https://forum.digilentinc.com/topic/18479-cmod-a7-vivado-2019-cannot-get-past-implementation/

我要求知道”进行存储guration program to Flash-memory” is solved by learning the “2. Creating Program File” of “Cmod A7 Programming Guide”. So, no need your answers for the Q1 and Q2. I'm sorry to interrupt you.

The Q2 statement is revised. [Wrong] Please let me know, How to show this pop-up? [Correct] Please let me know, How to show this “SREC SPI Bootloader” Templates? Actually, I am using a “Xilinx SDK 2019.1”.

Many thanks for your comments. I started to learn and handling of the CMOD-A7(35T) and the “blinky.v” is successfully worked on my CMOD-A7 (on Vivado 2016.4) based on the “Getting Started with Vivado”. Next, I am trying to store the project by referring the “How To Store Your SDK Project in SPI Flash”. https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start Q1: I did the “0. Compress Bitstreams (Optional)” (<-- check the “-bin_file*[V]” and set “Enable Bitstreem compression [TRUE]”), > 0.6) Now Vivado has been configured to output a compressed bitstream which will transfer to your SDK project. > Select [Generate Bitstreem] and a window might pop up asking you to save your XDC. If so, give the XDC a name and save it. Your bitstream should start generating afterwards. However the “window might pop up asking you to save your XDC” is not shown in my window. Please let me know, How to show this pop-up? Q2: On the following section of the “1. Create a SPI Bootloader Application”, > 1.2) Select SREC SPI Bootloader and select Finish. However, the “SREC SPI Bootloader” is not shown on the “Available Templates:”. Please let me know, How to show this pop-up? Thanks, T. Tamanuki

亲爱的zygot_san,非常感谢你的细节参考ts. I purchase ordered the Cmod-A7(35T) today and it will be shipped to us tomorrow. BTW, do you have reference FPGA-configuration program of SPI-driving-circuit? I would like to configurate the FPGA as “driving circuit of 8-slaves SPI (MOSI only)”. Also, do you have reference run-program (SRAM table) of the SPI-driver-configurated-FPGA? I would appreciate if you could provide them to me. Thanks.

Dear xc6lx45_san and zygot_san, Thank you very much for your detail comments about the FPGA-module product of Cmod A7 and Cmod S6. Actually, the AD2 is introduced into my existing SPI-circuit-system (8-slaves-SPI (MOSI): 16pcs-DACs are included in the each slave. That is 128pcs-DACs for 8-slaves.) and I am considering to introduce a FPGA into the programmable-control of SPI. Because, I am thinking that we can speed up the program-executing-time by introduction of FPGA instead of AD2 due to eliminate the USB-communication-time on the AD2-case. >> It has built-in PLLs so you can generate any frequency you like. > The CMOD A7 devices have clock management hardware so you can take any input clock and create a lot of different output clocks for your design. In my existing AD2-SPI-circuit-system, I am driving it with clock-speed of 10MHz. For my double checking, the CMOD A7 can create 10MHz SPI_clock (by PLL). On the other hand, the Cmod S6 can not create 10MHz-clock since it has no PLL. Am I right?