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你好！我对所有这些都是新手。我正在创建一个涉及JSTK2 PMOD的项目，现在我想在勤奋的GitHub上的示例代码单独测试PMOD，然后再将其集成到我的系统。但是，我被困在生成bitstream上。我已经在KYPD PMOD的另一个RTL项目中成功地完成了这项工作，没有问题。我将分享我的块设计的屏幕截图。我正在使用Zybo Z7-10，并且正在使用Vivado 2021.1。我使用此链接来帮助我开始我的IP：https：//www.knowreader.com/reference/lealen/lealen/programmable-logic/tutorials/pmod-ips/start，就像我提到的那样，它适用于KYPD PMOD。让我知道是否需要其他任何东西来帮助调试。以下是错误消息：[DRC NSTD-1]未指定的I/O标准：138个逻辑端口中的4个使用I/O标准（Iostandard）值'默认值'，而不是用户分配的特定值。 This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Pmod_out_0_pin10_io, Pmod_out_0_pin7_io, Pmod_out_0_pin8_io, and Pmod_out_0_pin9_io. [DRC UCIO-1] Unconstrained Logical Port: 4 out of 138 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Pmod_out_0_pin10_io, Pmod_out_0_pin7_io, Pmod_out_0_pin8_io, and Pmod_out_0_pin9_io. My assumption is that my constraints aren't defined properly but I am not sure where to go from there. Any advice/help would be greatly appreciated. Thank you!