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Hi I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good. I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong? The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some buttons and leds and the DDR3 memory controller. I'm using the latest IP version from the Digilent IP Repo. Thanks

我面临着如何在Nexys 4 DDR板中使用XADC向导的问题，我只想获得外部输入的数字转换，并直接访问12bits的数字输出。我是新手，目前，我正在尝试将XADC和12个DAC互连接，以将模拟输入（从函数生成器带走）转换为数字（将存储在FPGA中），然后使用该数字数据在DAC的输出处生成相同的信号。如果您可以解释/提供一个逐步的过程来进行操作，这将非常有帮助。您可以使用块设计或源代码来帮助您。

I'm trying to get the Pmod Color module for the Zynq z7-10 to work but it doesn't appear to be on. I was following along the instructions from these sites: https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start https://projects.digilentinc.com/arthur-brown/displaying-color-readings-with-the-pmod-color-and-python-ebd794 and I have it connect to the device as such on the board's JA port: Following along with the first link, I skipped the steps where a clock and interrupt were added as the data sheet shows that the Pmod Color IP does not require these. I have included my schematic below. I see that the module has an LED pin (LD1) but it doesn't appear to be on when connected to my powered device. In the SDK, I added a debug 'else' statement to the main() portion of the code to see if the Pmod is receiving data. After running the code on the board, the else statement is the only statement being executed. What could be the issue that my module is not turning on? I took a voltmeter reading, and the Vcc and GND pins are getting 3.3V. Following the instructions of the first link, I noticed they never included a constraints file. Could this be the issue? zynq_ps_main_c.c

大家好，我正在尝试在Vivado 2018.3中进行简单的IP块设计，以使用AT命令进行数据传输测试ESP32 PMOD。我将把我当前框图的图片附加到这篇文章中。我遇到了一个关键错误（以下参考），其中IP的包装板值为“ digilentinc.com：cora-Z7-10:part0:1.0”，该值适用于Zybo Z7板。我的问题是：Q1）无论此错误如何，这项设计工作是否会因为Zybo和ZED董事会相似，并且都从Zynq-7体系结构中运行？Q2）如果Q1的答案是“否”，是否有一种将此IP适应Zedboard的方法？（我应该使用Digilent的最新IP库）[IP_FLOW 19-4965] IP PMODESP32_AXI_GPIO_0_0包装带有板值'digilentinc.com：Cora-Z7-10:part0:1.0'。当前项目的董事会价值为“ digilentinc.com:zedboard：part0:1.0'。请更新项目设置以匹配包装的IP。

Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about adding an RTL module, which seemed more appropriate because I want to be able to modify quickly as I go, and in the same project. Based on what I've read, I was thinking to make an RTL module with a Slave AXI-lite interface (not sure how to do the registers though?), then use a master AXI-stream to pump the results to a Xilinx DMA IP block. I've been passing Synthesis but getting different Implementation errors ("failed to stitch checkpoint", "*.vhd is a black box") doing trial and error with this. All I've done in terms of the code is try to define the entity port to have those two interfaces, either copying from other IPs or using the Language Template (for AXI stream). Is there a good example in VHDL of a barebones AXI peripheral like this, that will pass Implementation? Once that works, I can get into adding those registers and the processing logic. Thank you!

你好所有的,我一直在做一个音频循环project which requires DDR3 memory for audio sample storage. After setting up the MIG-7 according to the Nexys Video Reference Sec 3.1 and reading through the 7 Series FPGAs Memory Interface Solutions User Guide, I'm at a loss for why the memory component won't initialize. I'm including a link to my repo here, but I'll try to explain my implementation in detail below: Clocking: Using the settings recommended here by @elodg, I set up an IBUFG in my top level file, feeding a clk_wiz instantiation in the file containing my MIG. This also involved setting up a clock backbone route in my constraint file. Instantiation: I've been instantiating my MIG with inputs set to 0 (except clocks) and outputs left open, just trying to get that init_calib_complete signal to go high. clk1 : clk_wiz_0 port map ( -- Clock out ports clk_out1 => clk_ref, -- Status and control signals resetn => reset_n, -- Clock in ports clk_in1 => sys_clk_ibufg); u_mig_7 : mig_7 port map ( -- Memory interface ports ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cas_n => ddr3_cas_n, ddr3_ck_n => ddr3_ck_n, ddr3_ck_p => ddr3_ck_p, ddr3_cke => ddr3_cke, ddr3_ras_n => ddr3_ras_n, ddr3_reset_n => ddr3_reset_n, ddr3_we_n => ddr3_we_n, ddr3_dq => ddr3_dq, ddr3_dqs_n => ddr3_dqs_n, ddr3_dqs_p => ddr3_dqs_p, init_calib_complete => init_calib_complete, ddr3_odt => ddr3_odt, -- Application interface ports app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => (others => '0'), app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => open, app_rd_data_valid => open, app_rdy => open, app_wdf_rdy => open, app_sr_req => '0', app_ref_req => '0', app_zq_req => '0', app_sr_active => open, app_ref_ack => open, app_zq_ack => open, ui_clk => open, ui_clk_sync_rst => open, -- System Clock Ports sys_clk_i => sys_clk_ibufg, -- Reference Clock Ports clk_ref_i => clk_ref, sys_rst => reset_n ); Constraints: I have one user constraint file bringing in the 100MHz clock from the board as well as buttons, switches, leds, and the audio codec signals for debugging and other functionality. It's attached to this post. MIG setup wizard settings: If anyone has experience with using this MIG or any clocking expertise, please let me know. I've been banging my head against this just hoping for a calibration, and I would really appreciate your help. Thank you!