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我正在寻找DAC 1411数据表，以便可以找到SFDR（虚假的免费动态范围）规格。

大家好，我正在寻找ADC和DAC至少2个MSP和一个大于或等于12位的分辨率。我不想将ADC或DAC与FMC类型接口一起使用（我的FPGA卡上没有足够的免费引脚）。串行类型接口（SPI）会很好。是否有具有这些特征的PMOD？如果没有，您可以推荐具有这些特征的ADC / DAC（> 2 MSP和> 12位分辨率）吗？我必须处理频率<= 10 kHz的信号，并将其发送到DAC至少12位的分辨率和至少2个MSP的采集速度。谢谢！问候h

嗨，我是FPGA的新手。Xilinx Spartan 3E Nexys2 FPGA板是否包含内部ADC和DAC？如果是，哪个端口是？谢谢，问候，Divya

Hey Digilent, I've successfully run the low_level_zmod_adc_dac demo on my board with a ADC and DAC ZMOD. https://reference.digilentinc.com/reference/programmable-logic/eclypse-z7/low_level_zmod_adc_dac I next decided to run the zmod_dac demo using both petalinux and baremetal. https://github.com/Digilent/Eclypse-Z7/tree/zmod_dac/master I was able to program the FPGA and also run the code, however every time it attempts to allocate a buffer to transfer the waveform via AXI DMA malloc is returning a 0/NULL value for the buffer address. If I am correct this means that malloc is unable to obtain memory. I'm running this demo as is directly from your git repo. The error that occurs due to this 0 buffer address varies, for petalinux it causes a memory violation error when it tries to copy the waveform to the buffer. For bare metal it copies fine, but then the AXI DMA copy never completes presumably due to the bad 0 address. Do you have any tips for me on how to get this demo running? If there is any additional information I can provide just let me know. I did find it curious that fnAllocBuffer takes an "addr" corresponding to the dmaAddr on the zmod but then doesn't use it for anything, could that be related? Thanks! void* fnAllocBuffer(uintptr_t addr, size_t size) { uint32_t *buf = (uint32_t *)malloc(size); return buf; }

大家好,我想实现一个dac的例子into my fpga board (MYD-C7Z015). My input will be 32 bit. First 4 bits are command bit which are C3=0, C2=0, C1=1, C0=1. Next 4 bits are Don't Care Bits. After Don't Care Bits, 12 Bits will be nothing(space). Then the rest 16 bits will be my data.In other words, I try to implement LTC-2601 to 32 bit input. Now I have an IP with one output port. This Slave Ip has 4 registers. Also I use Zynq-7000 Processing System IP. In each rising edge of Zynq 7000 Processing System IP's clock I look at one bit and assign that bit to my slave register (in this example slv_reg0). Since my oscilloscope can measure up to 350 Mhz, I have to decrease the frequency of clock. That's why I just do this process in 20 rising edge of clock. In SDK part of my project, I just send some data to my slave register with Xil_Out32 function. However, after all this process the result is considerably different than I expected. My oscilloscope shows the only impulses. Also this part does not work properly. I expected a really nice square wave. But in the implementation it has some fluctuation in the wave. I leave my VHDL code below. Thank you. port( -- Users to add ports here output : out std_logic := '0'; -- User ports ends ); -- Add user logic here -- S_AXI_ACLK is the clock from Zynq-7000 Processing System IP. process(S_AXI_ACLK) variable index : integer := 0; variable counter: integer := 0; begin if rising_edge(S_AXI_ACLK) then case index is -- 4 Command Bits start when 0 => output <= '0'; when 1 => output <= '0'; when 2 => output <= '1'; when 3 => output <= '1'; -- 4 Command Bits end -- 4 Don't Care Bits start when 4 => output <= '0'; when 5 => output <= '0'; when 6 => output <= '0'; when 7 => output <= '0'; -- 4 Don't Care Bits end -- 16 Data Bits start when 8 => output <= slv_reg0(16); when 9 => output <= slv_reg0(17); when 10 => output <= slv_reg0(18); when 11 => output <= slv_reg0(19); when 12 => output <= slv_reg0(20); when 13 => output <= slv_reg0(21); when 14 => output <= slv_reg0(22); when 15 => output <= slv_reg0(23); when 16 => output <= slv_reg0(24); when 17 => output <= slv_reg0(25); when 18 => output <= slv_reg0(26); when 19 => output <= slv_reg0(27); when 20 => output <= slv_reg0(28); when 21 => output <= slv_reg0(29); when 22 => output <= slv_reg0(30); when 23 => output <= slv_reg0(31); -- Data Bits end when others => end case; if counter = 0 then index := (index + 1) mod 24; end if; counter:= ( counter +1) mod 20; end if; end process; -- User logic ends Note: This vhdl code is from my axi peripheral ip. The rest of the ports, entity, logic and etc is created by the ip itself. So I did not put them here.

大家好，在成功地使用Zybo Z7010板的DE XADC之后，我现在正在尝试使用DAC PMOD（在此处参考和文档）。检查了文档后，我尝试将SPI连接编写到DAC（请在附件文件中找到Verilog文件和仿真）。请注意，我已决定将L_DAC信号设置为0，以将连续输出启用到示波器。模拟似乎对我来说很好，并且要符合文档，但是结果并不令人满意。实际上，我要输出的信号是在16位上，命令“输出= 16'b111111111111111”，这应该给出最大值。此外，当我要求“输出= 16'B10000000000000”（应该给出最大信号的一半）时，输出几乎为零。最后，当我输入具有0.5V偏移和1VPP的正弦信号时，请在附加文件中找到我在示波器上获得的图像。Aybody看到我缺少什么吗？如果需要，请不要犹豫，询问更多细节。预先感谢您，dac_wiz_0.v dac_wiz_0.sim