PHDEV
PHDEV的成就
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名声
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Gopal Krishna对一个问题的答案做出了反应：FPGA的以太网端口访问
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我已经使用了FPGA-Cores.com的以太网核心已有几年了，它们可以毫无问题地工作。它们包含您将FPGA连接到以太网所需的一切。真的很容易使用。不需要处理器。他们可以免费下载。这里有一个教程Nexus板。仅当PHY连接到Zynq设备上的PL时，才有可能使用这些内核。
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嗨，我认为您应该看看即时SoC。这是解决您想做的事情的一种非常简单的方法。它将C/C ++编译到VHDL，并有用于UARTS等的类。您可以进行划分，截断等。它可以免费下载和使用。
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您是什么意思，因为您使用的是FC1002以太网核心TCP数据包数据将通过AXI流传输到逻辑。该流由您的逻辑使用。AXI流信号为TCP0_TXDATA，TCP0_TXVALID，TCP0_TXREADY用于传输数据和TCP0_RXDATA，TCP0_RXVALID，TCP0_RXRXRXRXRXRXRXRXRXRXRXRXRXRXRX REDY用于接收数据
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嗨，埃里克。如果您喜欢C ++，我建议您查看Instant-Soc。它根据您的C ++代码生成所需的硬件。我尚未使用Arty S7板使用它，但是我使用Arty A7使用了很多。在这里，您可以使用I2C类找到一个示例。
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嗨，我做了一个使用Instant SoC的示例，它在项目保险库中。也许可以帮助您。https://forum.digilentinc.com/topic/18420-risc-v-on-nexys/
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@Jay D我建议您查看本教程。此核心执行所有以太网协议（ARP，DHCP，UDP，TCP，ICMP等），而无需使用任何操作系统或额外的内存。我一直都在使用它，没有发现任何问题。您可以免费下载并使用它。远程程序员也效果很好。如果您像我一样进行任何信号处理，还有一个远程逻辑分析仪，可以作为内部示波器效果很好。
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嗨，@NTM，我认为您应该查看此示例：在示例中，我使用新的Instant SOC / RISC V工具。现在，当我像您所描述的项目一样进行较小的项目时，我将使用它而不是微衬里。输出为VHDL，但是还生成了Verilog包装器。
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I tried the new Instant SoC from FPGA Cores on my Nexys 4 DDR (Nexys A7) board. Instant SoC is a C++ compiler that compiles C++ directly to a RISC-V processor and peripherals. The result is one vhdl file that I synthesized with Vivado. The only file I needed to add was the constraints file to map the signals to pins. The code implements a simple inclinometer. This is a description of what the code does: Sleeps 100 ms Read accelerations from the on board accelerometer using SPI Calculates angles using floating point math (atan, sqrt) Removes the zero offset that is reset using the center button. Print angles with one decimal point on UART Set the angles on 7 segment display Calculates an effect on the 16-leds. A led is “rolling” to the direction the board is leaning. Repeat A lot of the code was taken from Instant SoC class lib doc. The "hardware section", first in the main file defines the IO etc. In this case I created the following objects: ... int main(void) { //% hw_begin FC_IO_Clk Clk(100); FC_IO_Out LED(16); FC_IO_SPI accel(1000000,0,8); FC_IO_UART_TX uart_tx(115200,32); FC_IO_SegmentDisplay s7(8,8,0); FC_IO_In button_center; FC_System_Timer timer; //% hw_end uart_tx << "\r\nInclinometer demo using Nexys\r\n"; ... When compiling this it resulted in a VHDL file with the following port signals: ... entity nexys is port( Clk : in std_logic; LED : out std_logic_vector(15 downto 0); accel_SCLK : out std_logic; accel_MOSI : out std_logic; accel_MISO : in std_logic; accel_SSn : out std_logic; uart_tx : out std_logic; s7_seg : out std_logic_vector(7 downto 0); s7_sel : out std_logic_vector(7 downto 0); button_center : in std_logic ); end entity; architecture IMPL of nexys is ... And if you prefer Verilog there is also a Verilog header file generated: ... module nexys( input Clk, output [15:0] LED, output accel_SCLK, output accel_MOSI, input accel_MISO, output accel_SSn, output uart_tx, output [7:0] s7_seg, output [7:0] s7_sel, input button_center ); endmodule ... The system is free to download. I have attached the bit file (zipped) so it is possible to see what the C++ does. nexys.cpp nexys.xdc nexys_bit.zip
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@D@n是的我认为他们伟大的工作。非常容易使用. I have mostly been using FC1002 with TCP. I have also used FC1003 in a project where UDP (broadcast) was a better choice. I hope they release a FC1004 with RMII: (Both UDP and TCP) DHCP or fix IP works as expected. The remote programmer also works very good. I think it is faster and easier than using XIlinx programming tools. The logic analyzer is also very useful for debugging the system without using the jtag. Only bad thing is that I sometimes need larger sample buffers. I also miss some documentation, however I think I have figured it out most of it now. I really like the AXI-stream. Xilinx has very good components supporting this like clock domain crossing, FIFO, Filters etc.