Skinnypanda

惊人的！谢谢！

In asic design, I just put a request into our libary person to build a RAM the size I need, and get a module back with some behavioral code underneath. Not sure how it works in zedboard/vivado. I need a 4k x 16bit ram. and a much smaller 16 deep x 32bit wide ram. i coded them for a read port and a write port, but I could combine into one port if that helps. It needs to run at 100mhz. the 16x32 might be able to be built with flops. But I doubt the 4k block can be done in flops. do you just try to synthesize to see if flops will work? reg [31:0] smallram [15:0]; reg [15:0] bigram [4095:0]; Are there some modules that let me instantiate the underlying ram cells in the zedboard? I tried googling for zedboard block ram and found somethign that generates ram blocks with axi interfaces? That was more complicated than I needed. I was hoping for a paramaterized module that lets me specify width and depth? and a straightforward write/read bus, not AXI interface. I don't even know what to google. do you call that a block ram in vivado/zedboard speak? If this is already answered/explained somewhere else, just point me to it and I'll go there. thanks

“我不得不做一些挖掘才能找到它们。”我根本找不到任何东西。有时候这些东西有些晦涩，这有点奇怪。“ userInput = xuartps_readreg（XPAR_PS7_UART_0_BASEADDR，XUARTPS_FIFO_OFFSET）;”是的，这很晦涩。;）但是我能够使这个工作。十行代码和两个非常晦涩的呼叫，它正在做我需要的事情。谢谢您的帮助。

Zygot:"Frankly if either of us has been abusive, it's been you. You are the only one slinging personal attacks." Yeah, lets do the instant replay: "What should we think of someone who asks for help, and oh by the way if this is complicated can I have a step by step tutorial, because my time is too important to find the answers for myself. And then, to the first person willing to give up his time to reply gets a 'how hard can it be?' retort? You wanna provide the punchline or should I?" There's an implication here that I am lazy, too important to google, and ungrateful enough to give a "retort". Unless the "punchline" was something complimentary? Yeah, no... That entire paragraph is the first salvo of personal attacks in this thread. You started this thread towards personal attacks. Not me. All i've done is ask a question, attempt to clarify that question after you misunderstood it, and then pointed out the above paragraph is when this thread started the personal attacks. The only time i ever said anything about you personally was when i pointed to your comments that were making personal attacks against me. Oh, and attacking someone by saying i think "my time is too important" and then pretending i am somehow "inferring things that aren't implied or explicitly written"? That is called gaslighting. You were very clear there, i think my time is too important, quite explicit, very personal, and when called on it, you pretend none of it happened. Gaslighting is when someone attacks and then tries to rewrite and rearrange history so they are the victim. So, a personal attack, followed by gaslighting. And the only thing i have said on this thread about you is pointing out where you started this thread down the path of personal attacks.

您误读了我的问题，以什么才能被毒性为有毒的回应。您对“讽刺幽默”的援引降落时，有人说“所有的乐趣！”虐待之后。我已经担任工程师数十年了。大部分是ASIC的工作。我对FPGA非常生锈。但是我不是傻瓜。而且，您越早得到人们的哑巴，而不是问一个问题，那么您就会越好。

“然后，对于愿意放弃时间回复的第一个人，'有多难吗？'反驳？”您说“您有解析用户输入”。后来，您说：“您将进入弦和转换，谁知道什么……”但是，这比我想要的要复杂。我不需要解析任何内容或处理创建字符串类。我试图通过问：“打印某些东西，然后寻找用户的“ y”或“ n”，这是一个更基本的问题？”显然，这里发生了一种误解，这是澄清的合法尝试。“我可以逐步教程，因为我的时间太重要了，无法为自己找到答案。”您完全倒退了。我说：“如果它复杂，有人可以将我指向某个地方的教程吗？”就像在那样，如果它复杂，但已经覆盖了某个地方，那么您的时间太重要了，不愿意将其解释给像我这样的菜鸟，只需张贴URL，我就会涉足在那里的答案。 this appears to be a continuation of the whole misunderstanding going on in this thread

打印某些东西，然后从用户那里寻找“ y”或“ n”有多困难？我会有一个小循环检查是否有输入，并在存在时退出循环。然后获取角色，看看它是“ y”还是“ n”。int答案；int wait4answer = 1;while（wait4answer）{int wait4keyboard = 1;while（wait4keyboard）{wait4keyboard = some_function_to_check_if_serial_data_available（）;} int char = some_function_to_get_serial_character（）;if（（char =='y'）||（char =='n'））{anders = char;wait4answer = 0; } } DO_SOMETHING_WITH_ANSWER(answer); I've done something like this on simple microcontroller projects before. I just need to know what the SOME_FUNCTION_TO_CHECK_IF_SERIAL_DATA_AVAILABLE() and SOME_FUNCTION_TO_GET_SERIAL_CHARACTER() functions are called, assuming they exist. It doesn't have to present a shell type interface, it doesn't have to support up-arrow to get previous commands, or backspace to edit the current line of text, it doesn't have to do auto-complete when "tab" is hit.

I stepped through this tutorial and got it to work: http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/HwSw_dr/VivadoEmbeddedZyncTutorialAddIP.pdf It's a bare metal project that does writes and reads to a simple custom AXI IP block and then prints some info and results to serial terminal. I connect to zedboard with PUTTY on my PC, and when I run the code in vitis, it dumps a bunch of info to the terminal by calling print(). My question is how do I tweak this to do serial READ from the user serial terminal, but keep everything pretty much the same? If its complicated, could someone point me to a tutorial somewhere? I'm using vivado 2020.1, if that makes any difference. Thanks.

LED眨眼，串行端口正在谈论！哦，伙计，这感觉很好。再次感谢您的帮助。

我删除了所有内容，并开始了教程。我确保每次vivado都要求我命名文件之类的东西时，我都会用“ vivado_”将其前缀。每个vitis的名称都带有“ vitis_​​”。它给了我一个构建。不知道在哪里，但是我必须在现有文件的顶部命名一些东西，并安静地搞砸了东西。谢谢您的帮助！

只是给自己一个Zedboard。丝绸屏幕上说“ 2020年版权”，因此相当新。我在这里浏览说明：https：//reference.digilentinc.com/programmable-logic/guides/guides/getting-started-with-ipi，我正在使用vivado v2020.1（64位）和xilinx visity vitis IDE IDEV2020.1.0（64位），因为这似乎是该教程的推荐版本。我尝试了以后的版本，许多屏幕截图完全不同。当我进入Vitis时，我会在助理窗格中选择系统项目，然后单击“构建”按钮（Hammer）。我在“问题”选项卡下获取以下内容：描述资源路径位置类型致命错误：xgpio.h：no oke file或目录main.c/project_1_app/src行3 c/c ++问题。：package]错误1 debug /project_1_app_system c /c ++问题当我查看vitis.log选项卡时，我会看到以下内容，withi zed.xsa错误在底部：12:45：48 debug：注册sdkstatushandler来处理跟踪excepies。12:45:48调试：将核心插件注册为用于存储存储库路径的备份插件。12:45:48信息：启动XSCT服务器：XSCT.BAT -N -Interactive D：\ Workspace \ temp_xsdb_launch_script.tcl 12:45:48信息：XSCT服务器已成功启动。 12:45:48 INFO : plnx-install-location is set to '' 12:45:48 INFO : Successfully done setting XSCT server connection channel 12:45:48 INFO : Successfully done setting workspace for the tool. 12:45:48 INFO : Platform repository initialization has completed. 12:45:48 INFO : Registering command handlers for Vitis TCF services 12:45:48 INFO : Successfully done query RDI_DATADIR 12:45:57 INFO : Checking for BSP changes to sync application flags for project 'project_1_app'... 12:46:03 ERROR : (XSDB Server)ERROR: [Hsi 55-1571] The design file D:/workspace/project_1_wrapper/export/project_1_wrapper/hw/zed.xsa is already opened at which point, the Vitis.log stops there. I've seen the "fatal error: xgpio.h: No such file or directory" on other posts this forum and elsewhere, but I have not seen a definitive answer to how to fix it. The only specific "try this" thing I've seen is try refreshing and try going back to vivado and rerun synthesis, implementation, and bitstream. Neither fixed the problem for me. I followed these instructions to download board files: https://reference.digilentinc.com/programmable-logic/guides/installation I copied the "new/board files" because instructions say that is for versions later than 2014.4 And when I google for "zed.xsa is already opened", I don't find it anywhere. any help would be appreciated