soufyane

嗨，我购买了PMOD RF2，我想知道您在PMODS库中是否有IP设计？感谢您的答复Soufyane

嗨，@jcolvin，现在正在工作！！！我在Vitis中重新创建了App +平台，它起作用。

嗨@jcolvin这是我的设计design_1.pdf

嗨@JColvin我编程成功Zybo但it stope (crash) at addPins(vitis : addPins(XPAR_AXI_GPIO_0_BASEADDR, 4, 0) : line 109 deWebIOServerSrc.cpp). I saw that when I launch the program in debug mode .

HI @jcolvin，在Vivado 19您无法重命名Axi-GPIO IP。您有什么建议，为什么它会在Addpin中摇摆吗？

Hi im trying to interface pmod wifi on zybo board, i followed the instructions in youtube video tutorial for pmodwifi but i dont have AXI_GPIO LED in xparameters.h How i can add pin led and switch to AXI_GPIO if they are not defined in xparameters.h . do you changed that?? im using Vitis2019.

I solved makefile error by changing outs by objects OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) by I still have undefined reference error

仍然无法使用Vitis 2020更新的Zybo IM上的pmodwifi接口pmodwifi 1我认为它的vity vitis fipy 2020上有任何变化，我遇到了所有这些错误：

我找到了一个解决方案。进行更改和重建后，您只需要重新出口硬件。PMOD Gyro现在在我的Zybo上工作。您必须在GitHub中的Make File上对IP存储库进行一些更改。他们更改了如何参考Vitis 2020上的对象文件

I found a workaround; it seems that they changed how to refer to object files Solution : change (outs) with objects $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) but i still have some problems in makefile with PmodGyro the App not compiling Can you have a look to this Pb ?? make all Generating bif file for the system project generate_system_bif.bat 49917 C:/Users/NZT/workspace/design_1_wrapper/export/design_1_wrapper/design_1_wrapper.xpfm domain_ps7_cortexa9_0 C:/Users/NZT/workspace/testGyro2App_system/Debug/system.bif sdcard_gen --xpfm C:/Users/NZT/workspace/design_1_wrapper/export/design_1_wrapper/design_1_wrapper.xpfm --sys_config design_1_wrapper --bif C:/Users/NZT/workspace/testGyro2App_system/Debug/system.bif --bitstream C:/Users/NZT/workspace/testGyro2App/_ide/bitstream/design_1_wrapper.bit --elf C:/Users/NZT/workspace/testGyro2App/Debug/testGyro2App.elf,ps7_cortexa9_0 creating BOOT.BIN using C:/Users/NZT/workspace/testGyro2App/_ide/bitstream/design_1_wrapper.bit Error intializing SD boot data : Software platform XML error, sdx:qemuArguments value "design_1_wrapper/qemu/qemu_args.txt" path does not exist C:/Users/NZT/workspace/design_1_wrapper/export/design_1_wrapper/sw/design_1_wrapper/qemu/qemu_args.txt, platform path C:/Users/NZT/workspace/design_1_wrapper/export/design_1_wrapper, sdx:configuration design_1_wrapper, sdx:image standard make: *** [makefile:39: package] Error 1 19:50:35 Build Finished (took 5s.778ms)

嗨，我正在使用Zybo 7020 Vivado/Vitis 2020，当我编译HW平台时，我会出现一些错误。“在PS7_Cortexa9_0/libsrc/pmodgyro_v1_0/src中运行libs” make -c ps7_cortexa9_0/libsrc/pmodgyro_v1_0/src -s src -s libs libs libs libs libs libs libs shell = cmd = cmd = cmd = cmd = cmd = cmd compiler = arm-none-aone-eabi-gcc armebi armebi =-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta rtfiles -g -Wall -Wextra“ make [2]：输入目录'c：/user/nzt/workspace/gyrotest/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/pmodgyro_v1_0/src'：无效参数make [2]：*** [makefile：19：libs]错误1 make [1]：*** [makefile：30：ps7_cortexa9_0/libsrc/pmodgyro_v1_0/src/src/make.libs]错误2** [Makefile:30: zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a] Error 2 make[2]: Leaving directory 'C:/Users/NZT/workspace/Gyrotest/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src'make [1]：离开目录'c：/user/nzt/workspace/gyrotest/zynq_fsbl/zynq_fsbl_bsp'构建bsp库的bsp库 - standalone_domain在处理器ps7_cortexa9_0上，“运行制作都包括在ps7_cortexa9_0/libsrc/coresightps_dcc_dcc_v1_7/src”中“”“编译器= ARM-NONE-AEBI-GCC”“ assembler = Arm-None-eabi-as”“ Archiver = Arm-None-None-Aebi-ar”“ Compiler_flags = -O2 -C”“ Extra_compiler_flags = -mcpu = -mcpu = cortex--cortex--cortex--a9 -mfpu = vfpv3 -mfloat -abi = hard -nosta rtfiles -g -wall -wextra“”“编译pmodgyro ...” Arm -None -eabi -ar： *.o： *.o：无效参数make make [1]：***[makefile：19：libs]错误1 make：*** [makefile：30：ps7_cortexa9_0/libsrc/pmodgyro_v1_0/src/make.libs]错误2未能构建域的BSP来源-AstalOne_domain无法生成该平台。原因：无法构建zynq_fsbl应用程序。从“ :: tcf :: eval -progress {apply {{msg} {puts $ msg}}}} {tcf_send_command tcfchan＃0 xsdb eval s es {{platform active gyrotest; platform generate}}}”（Procesture'（过程）：tcf :: send_command“第4行）从“ tcf send_command” $ :: xsdb :: curochan xsdb eval s es [list'platform active $ platflation $ planction_name;平台生成$ target“]”从内部调用”，如果{$ iswindows == 1} {set xsdb_port [lindex $ argv 0] set platform_name [lindex $ argv 1] set arglen [llength $ argv] set last tast last ...file "C:/Xilinx/Vitis/2020.1\scripts\vitis\util\buildplatform.tcl" line 11) I thinks there is some problems in the makefile the error comes from this line in makefile $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} I downloaded the Library from github

我正在使用Vivado 2020

Hi im beginner on vivado, i have some troubles to interface the pmod wifi on zybo board. have you any tutorial how to do that on zybo board ?? thanks for your response

Thanks @JColvin for your replay

is there a video how to use pmod shield ??