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| programmable-logic:guides:vivado-validate-block-design [2021/06/15 18:37] Arthur Brown[Validate a Block Design] |
programmable-logic:guides:vivado-validate-block-design [2021/06/15 23:58](当前) Arthur Brown |
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| If there are no issues, a dialog will pop up that will tell you so. Click **OK** to continue. | If there are no issues, a dialog will pop up that will tell you so. Click **OK** to continue. | ||
| - | **Note:** //Some Zynq boards may produce critical warnings at this stage relating to PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY parameters. These warnings are ignorable and will not affect the functionality of the project. See the Hardware Errata section of your board'sresource centerfor more information.// | + | **Note:** //Some Zynq boards may produce critical warnings at this stage relating to PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY parameters. These warnings are ignorable and will not affect the functionality of the project. See the Hardware Errata section of your board'sreference manualfor more information.// |
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